Inrush currents must be minimized to avoid large voltage drops on the supply that can cause the system to lock or reset. The use of large decoupling capacitors in parallel to the supply can limit the effect of inrush but requires an increased area on printed boards.
Other integrated solutions addressing the problem might be less effective when the tolerance of external components and the effects of Process, Voltage and Temperature (PVT) variations come into picture.
Therefore it is a challenge for engineers to design LDOs having a limited inrush current in spite of PVT tolerances of components such as an external capacitor.